Extracting Logical Formulae that Capture the Functionality of SystemC Designs

Object-oriented hardware design languages like SystemC have become very popular to co-design hardware and software systems. Such designs are classically translated into a transition system in order to verify a specification with model-checkers. However, compositionnality and parametricity of SystemC components complicate their translations into finite transition systems. Processing analysis of high-level designs occurs early in the design flow and aims to greatly reduce the correction costs of eventual errors. In this paper, we propose a formal method to statically analyze SystemC designs. Our approach consists in extracting a logical formula representing the behavior of the system in order to avoid combinatorial explosion. This method combines a symbolic execution of SystemC code to infer logical formulae representing its behavior and a generalization phase of these inferred logical properties.